The present invention relates in general to resistors formed in metal oxide semiconductor (MOS) integrated circuit (IC) processes and, more particularly, to self-aligned resistors that are highly matched, compact, and exhibit reduced parasitic leakage, and to methods of making these resistors.
Many IC applications require the use of matched resistors. In such instances, it is important that the resistors formed into the IC are accurate and use as little substrate area as possible.
Presently, individual matched resistors in metal oxide semiconductor (MOS) processes are formed into a well region within a substrate using an active area mask and a dopant mask. More particularly, a plurality of active areas are delineated on the surface of the well region by growing a plurality of thick field oxide regions. A gate oxide film is placed over the active areas and the thick field oxide regions in order to form the gate insulator of MOS transistors. Strips of polysilicon can be placed over the portions of the gate oxide film that covers the thick field oxide regions, and biased with a voltage to help prevent leakage. Then, dopant material is implanted into the active areas of the well region, through individual windows formed in the dopant mask, to form the individual resistor bodies.
The resistors formed using the above-described process suffer several disadvantages. First, the resistors suffer width variations due to the so-called xe2x80x9cbird""s beakxe2x80x9d at the edges of the active areas. xe2x80x9cBird""s beakxe2x80x9d is a nonlinear oxide thinning caused by the various MOS fabrication steps. As a result of these width variations, the absolute and relative accuracy of the resistors is reduced. A second disadvantage is that parasitic leakage reduction between the resistor bodies is less than optimum. Although a voltage potential is applied to the polysilicon strips to inhibit such parasitic leakage, the polysilicon strips are each positioned above the thick field oxide regions thus providing limited parasitic leakage reduction effect. A third disadvantage is that the substrate area consumed by the resistors and associated well structure is less than optimum. This is because the total area consumed by the resistors is dependent on design rule spacing requirements, as defined by process capability. Specifically, the width dimension consumed by a single resistor includes the active area width (i.e., width of the resistor), a dopant mask overlap width on each side of the active area, and the spacing between the next resistor. The dopant mask overlap width dimension is necessary to take into account the manufacturing tolerances of the equipment being used to align the dopant and active area masks.
Hence, there is a need for a matched self-aligned resistor structure that does not suffer the accuracy reducing effects due to xe2x80x9cbird""s beak,xe2x80x9d that optimally reduces parasitic leakage between resistor bodies, and that consumes less substrate area.